8.clamping circuit theorem

Since i got a post on clamping circuits saying that he needs clear explanation on clamping circuit theorem

im posting it form a website which i really donot but i would post proof along with examples so that u understand better way and have command of theorem


Thankyou for posting.

This theorem enables us to calculate the voltage level to which the output is clamped by considering the areas above and below the reference level, when the values of R_f and R are known.

The clamping circuit theorem states that under steady-state conditions, for any input waveform, the ratio of the area under the output voltage curve in the forward direction to that in the reverse direction is equal to the ratio R_f/R. To prove the clamping circuit theorem, consider a typical steady-state output for the clamping circuit, represented in Fig. 5.31.

In the time interval t₁ to t₂, D is ON. Hence, during this period, the charge builds up on the capacitor C. If i_f is the diode current, the charge gained by the capacitor during the interval t₁ to t₂ is:

However, i_f = V_f/R_f, where V_f is the diode forward voltage:

During the interval t₂ to t₃, D is OFF. Hence, the capacitor discharges and the charge lost by C is:

FIGURE 5.31 Typical steady-state output of the clamping circuit

Put i_r = V_r/R, where V_r is the diode reverse voltage:

At steady state, the charge gained is equal to the charge lost. In other words, q₁ = q₂.

Therefore,

However,

FIGURE 5.32 The output of the clamping circuit when C is large

Here, A_f is the area with D in the ON state and A_r is the area under the output curve with D in the OFF state.

From Eqs. (5.47) and (5.48):

This relation is known as the clamping circuit theorem.

Consider Fig. 5.32 in which the output of the clamping circuit is assumed to remain almost constant during the periods T₁ and T₂ when the diode D is ON and OFF by choosing large values of C.

If V₁ and T₁ are the voltage and time duration above the reference level and V₂ and T₂ are the voltage and time duration below the reference level under steady-state, then as per this theorem:

Assuming that T₁, T₂, R_f, R and the amplitude of the signal V are known, it is possible to compute the voltage level V₁ to which the signal is clamped at the output.

SOLVED PROBLEMS

Example 5.8: The input shown in Fig. 5.33(a) is applied to the clamping circuit [see Fig. 5.33(b)]. Plot the output waveform. Given that R_s = R_f = 50 Ω, R = 10 kΩ, R_r = ∞, C = 1μF

FIGURE 5.33(a) The given Input; and (b) the given clamping circuit

Solution: The equivalent circuit, when the diode conducts, is shown in Fig. 5.34(a). When the diode does not conduct, the equivalent circuit is as shown in Fig. 5.34(b).

FIGURE 5.34(a) The equivalent circuit when D is ON

FIGURE 5.34(b) The equivalent circuit when D is OFF

1. At t = 0.1 ms, v_s abruptly rises to 8 V. As the capacitor cannot allow sudden changes in the voltage it behaves as a short circuit. 
   
2. The input remains constant at 8 V from 0.1 to 0.2 ms. So v_o decays exponentially with time constant (R_s + R_f) C.
   At t = 0.2 ms
   v_o = 4 e^{−0.1×10−3/(50+50)(1×10−6)} = 4e⁻¹ = 1.47152 V
   Voltage across the capacitor = v_A = 8 − 2 × 1.47152 = 5.05696 V
3. At t = 0.2 ms, v_s abruptly falls to −5 V. The resultant circuit is as shown in Fig. 5.34(c).
   
   
   v_o = −5 − 5.05696 = −10.05696 V
4. From t = 0.2 ms to 0.3 ms, v_s remains at −5 V. Hence, the output voltage should decay exponentially with a time constant (R + R_s) C.
   At 0.3 ms,
   v_o = −10.05696 e^{−0.1×10−3/(10000+50)(1×10−6)} = −9.958 V
   Voltage across C = v_A = −5 + 9.958 = 4.958 V
5. At t = 0.3 ms and v_s = 5 V. The equivalent circuit to be considered is shown in Fig. 5.34(d). 
   

FIGURE 5.34(c) The circuit to calculate the output

As v_s remains constant, v_o decays exponentially from t = 0.3 ms to 0.4 ms.

At t = 0.4 ms v_o = 0.0213 e⁻¹ ≈ 0 V. The output voltage now varies as shown in Fig. 5.34(e).

FIGURE 5.34(d) The circuit to calculate the output

FIGURE 5.34(e) The steady-state output waveform

Example 5.9: A clamping circuit and the input applied to it are shown in Fig. 5.35(a) and (b). Calculate and plot to scale the steady-state output. Given that: R_s = R_f = 100 Ω, T₁ = T₂ = 500 μs.

Solution: To calculate the steady-state voltages, first calculate V₁, , V₂ and  by making V_R = 0. During the interval 0 to T₁, the charging time constant of the capacitor C is:

τ_f = (R_s + R_f) C = (100 + 100)0.5 × 10⁻⁶ = 100 μs

The capacitor discharges during the interval T₁ to T₂ and the time constant, τ_r, is:

τ_r = (R_s + R)C = (100 + 200000)0.5 × 10⁻⁶ = 100050 μs = 100.050 ms

FIGURE 5.35(a) The given input; and (b) clamping circuit

FIGURE 5.35(c) The steady-state output

Also,

Solving Eqs. (1), (2), (3) and (4):

V₁ = 0.2516 V,         = 0.0017 V        V₂ = −99.996 V         = −99.496 V

To get the steady-state output, we add V_R to the values of V₁, , V₂ and  for the given circuit in Fig. 5.35(a). Therefore,

V₁ = 5.2516 V         = 5.0017 V        V₂ = −94.996 V         = −94.496 V.

The steady-state output is as shown in Fig. 5.35(c).

Example 5.10: Draw the output waveform under the steady state for the given biased clamping circuit shown in Fig. 5.36, when the input is 10 V square wave. Assume that C is very large so that the change in the output voltages during the periods when D is ON and OFF is negligible.

FIGURE 5.36 The given biased negative clamper with V_R = 5 V and the corresponding input and output waveforms

Solution: The diode D conducts when the input changes to +10 V. Then capacitor charges to +5 V after few cycles.

Under steady-state conditions v_o = v_s − v_A = v_s − 5

When v_s = 10 V, v_o = 10 − 5 = 5 V

When v_s = −10 V, v_o = −10 − 5 = −15 V

The positive peak is clamped to V_R(= 5V), in the output.

SUMMARY

• The dc component, that is blocked when a signal passes through a capacitive coupling network can again be restored using a clamping circuit.
• A clamping circuit, generally, is called a dc restorer and dc re-inserter, meaning that it reintroduces exactly the same amount of dc voltage lost. However, it is a dc inserter, which means that it introduces any desired dc voltage.
• A simple clamping circuit consists of a signal source, a capacitor of appropriate value and a diode connected across the output terminals.
• The positive or negative extremity of an input signal can be clamped to a zero level or to an arbitrarily chosen reference level by using a clamping circuit.
• The dc level associated with the input signal has absolutely no say in determining the steady-state response of the clamping circuit.
• The clamping circuit theorem states that for any input waveform under steady-state conditions A_f/A_r= R_f/R.
• A synchronized clamping circuit is one in which the time of clamping is not determined by the signal but by a control signal which is in synchronization with the signal.